A Parallel Decimal Multiplier Based on a novel 4:2 Fully Redundant Decimal Adder

A fully redundant decimal adder and its application in parallel decimal multipliers

Decimal hardware arithmetic units have recently regained popularity, as there is now a high demand for high performance decimal arithmetic. We propose a novel method for carry-free addition of decimal numbers, where each equally weighted decimal digit pair of the two operands is partitioned into two weighted bit-sets. The arithmetic values of these bit-sets are evaluated, in parallel, for fast ...

Radix - 10 Parallel Decimal Multiplier

This paper introduces novel architecture for Radix-10 decimal multiplier. The new generation of highperformance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multiplier. The parallel generation of partial products is performed using signed-digit radix-10 recoding of the multiplier and a simplified set of multiplicand multiples. The reduction of p...

A Fast Combined Decimal Adder/Subtractor

An algorithm for a fast decimal addition is proposed. The addition is performed in two steps. First, the result of addition is produced in a decimal signed-digit format. Second, the decimal signed-digit result is converted into the non-redundant form BCD. The conversion uses a borrow generating scheme based on a parallel-prefix network. Using the flexible features of the decimal signed-digit re...

On high-performance parallel decimal fixed-point multiplier designs

Fully redundant decimal addition and subtraction using stored-unibit encoding

Decimal computer arithmetic is experiencing a revived popularity, and there is quest for highperformance decimal hardware units. Successful experiences on binary computer arithmetic may find grounds in decimal arithmetic. For example, the traditional fully redundant (i.e., the result and both of the operands are represented in a redundant format) and semi-redundant (i.e., the result and only on...